1) Field of the Invention
The present invention relates to an apparatus which comprises a plurality of modules connected to one another in two or more modes (for example, a 64 bits transfer mode and a 32 bits transfer mode) through interface buses such as PCI (Peripheral Component Interconnect) buses or the like so that data can be transferred among the modules, and has a function of detecting abnormality of the data transfer mode among these modules. More concretely, the present invention is applied to a storage controlling apparatus disposed between a physical device (for example, a magnetic disk unit) and a host to control an access from the host to the physical device, and an interface module (for example, a host interface module or a disk interface module) used in the storage controlling apparatus.
2) Description of the Related Art
FIG. 4 is a block diagram showing a structure of a known storage apparatus (storage controlling apparatus). A storage apparatus 1 shown in FIG. 4 writes data from a server (host), and reads data requested by the server 4 and transfers the data to the server 4 in response to an access from the server 4.
The storage apparatus 1 comprises a disk enclosure 2 having a plurality of disk units (physical devices) 2a, and a storage controlling apparatus 3 disposed between the disk units 2a and the server 4 to control an access from the server 4 to each of the disk units 2a. 
The storage controlling apparatus 3 comprises a disk interface module 10, a host interface module 20, a management module 30 and a PCI bridge module 40.
The disk interface module 10 controls an interface (data transfer) with each of the disk units 2a in the disk enclosure 2 through a disk interface bus 54.
The host interface module 20 controls an interface (data transfer) with the server 4 through a fiber channel interface 50.
The management module 30 generally manages the whole of the storage controlling apparatus 3. The management module 30 is equipped with a cache memory temporarily storing data to be written in one of the disk units 2a from the server 4 or data to be read out from one of the disk units 2a to the server 4, and manages the cache memory.
The PCI bridge module 40 is connected thereto the disk interface module 10, the host interface module 20 and the management module 30 through PCI buses (interface buses) 51, 52 and 53 to connect the disk interface module 10, the host interface module 20 and the management module 30 to one another so that data can be transferred among them.
In the above structure, data writing from the server 4 to one of the disk units 2a and data reading from one of the disk units 2a to the server 4 are carried out as follows.
When data is written from the server 4 into one of the disk units 2a in the disk enclosure 2, the data to be written is transferred from the server 4 to the host interface module 20 through the fiber channel interface 50, and temporarily stored in the cache memory of the management module 30 from the host interface module 20 via the PCI bridge module 40 through the PCI buses 52 and 53, (refer to an arrow A1 in FIG. 4). After that, the data to be written stored in the cache memory of the management module 30 is transferred to the disk interface module 10 via the PCI bridge module 40 through the PCI buses 53 and 51, and written in a predetermined disk unit 2a from the disk interface module 10 through the disk interface bus 54 (refer to an arrow A2 in FIG. 4).
Conversely, when data is read out from one of the disk units 2a in the disk enclosure 2 to the server 4, the data to be read out is transferred from a disk unit 2a retaining the data to the disk interface module 10 through the disk interface bus 54, and temporarily stored from the disk interface module 10 in the cache memory of the management module 30 via the PCI bridge module 40 through the PCI buses 51 and 53 (refer to an arrow A3 in FIG. 4). After that, the data to be read out stored in the cache memory of the management module 30 is transferred to the host interface module 20 via the PCI bridge module 40 through the PCI buses 53 and 52, and read out to the server 4 from the host interface module 20 through the fiber channel interface 50 (refer to an arrow A4 in FIG. 4).
Next, description will be made of structures of the disk interface module 10 and the host interface module 20 in the storage controlling apparatus 3 shown in FIG. 4, with reference to a block diagram shown in FIG. 5. The disk interface module 10 and the host interface module 20 have basically the same structure. However, the host interface module 20 differs from the disk interface module 10 in that the host interface module 20 has a function of converting an optical signal from the fiber channel interface 50 into an electric signal and a function of converting an electric signal in the host interface module 10 into an optical signal and sending the optical signal to the fiber channel interface 50, while the disk interface module 10 does not have these functions.
As shown in FIG. 5, each of the disk interface module 10 and the host interface module 20 (hereinafter referred as interface modules 10 and 20, occasionally) comprises a CPU 11, a chip set 12, a memory 13, an interface module-LSI 14, a data buffer 15 and a fiber channel chip 16.
The CPU (Central Processing Unit) 11 fulfils a function of generally managing the interface module 10 or 20.
The chip set 12 has a function of connecting the CPU 11 to another device (for example, the memory 13) and a function of connecting the CPU 11 to the PCI bus 17. The CPU 11 is connected to the memory 13 via the chip set 12, and also connected to the interface module-LSI 14 via the chip set 12 through the PCI bus 17. The memory 13 is configured with, for example, an SDRAM (Synchronous Dynamic Random Access Memory).
The interface module-LSI (Large Scale Integration) 14 functions as a second transferring unit controlling data transfer between the interface module 10 or 20 and the PCI bridge module 40 through the PCI bus 51 or 52 according to an instruction from the CPU 11. The interface module-LSI 14 is provided with the data buffer 15.
The data buffer 15 is configured with, for example, a DDR (Double Data Rate)-SDRAM, which temporarily stores data to be transferred to the PCI bridge module 40 or data transferred from the PCI bridge module 40.
To the interface module-LSI 14, the PCI bridge module 40 is connected through the PCI bus 51 or 52, the chip set 12 is connected through the PCI bus (interface bus) 17, and the fiber channel chip 16 is connected through the PCI bus (interface bus) 18.
The interface module-LSI 14 has a function being as a DMAC (Direct Memory Access Controller). Normally, the CPU 11 runs a predetermined control program to set a descriptor in a DMAC in the interface module-LSI 14 to make the interface module-LSI 14 carry out data transfer.
The fiber channel chip (FC-Chip) 16 functions as a first transfer processing unit controlling data transfer between the interface module 10 or 20 and each of the disk units 2a or the server 4 through the fiber channel interface 50 or the disk interface bus 54.
In a system assumed to carry out large-capacity, high-speed data transfer (wide-band data transfer), a PCI bus having a width of 64 bits is generally used.
In the storage controlling apparatus 3 described above, PCI buses having a width of 64 bits are generally used as the PCI bus 18 connecting the interface module-LSI (module, second transfer processing unit) and the fiber channel chip (module, first transfer processing unit) 16 to each other, the PCI buses 51 and 52 connecting the interface module-LSI 14 and the PCI bridge module 40 to each other, and the PCI bus 53 connecting the management module 30 and the PCI bridge module 40 to each other in order to realize large-capacity, high-speed data transfer (wide-band data transfer). For this, standard chips (LSIs) coping with a width of 64 bits are used as the interface module-LSI 14, the fiber channel chip 16, the management module 30 and the PCI bridge module 40 connected to the PCI buses 51 through 53.
Since the width of 64 bits is expansion of a width of 32 bits in the PCI bus standard, the 64-bit PCI bus can carry out both 64-bit-wide data transfer (64-bit transfer mode) and 32-bit-wide data transfer (32-bit transfer mode). However, a system employing the 64-bit PCI bus is regularly operated in the 64-bit transfer mode, basically, in order to realize large-capacity, high-speed data transfer (wide-band data transfer).
In such the system, a predetermined transfer mode setting sequence (exchange of signals to set the 32-bit transfer mode or the 64-bit transfer mode; refer to FIGS. 6 and 7) is normally run at the time of resetting including the time of power-on or at the time of inter-module data transfer), and the 64-bit transfer mode is set each time.
Next, description will be made of a predetermined transfer mode setting sequence (a normal operation) in the interface module 10 or 20, with reference to a sequence diagram shown in FIG. 6. When the interface module 10 or 20 is reset (including the time of power-on), or when data is transferred between the interface module-LSI 14 and the fiber channel chip 16, or when data is transferred between the interface module-LSI 14 (the interface module 10 or 20) and the PCI bridge module 40, the interface module-LSI 14 asserts an REQ64 signal so that a request to set a connection in the 64-bit transfer mode is notified from the interface module-LSI 14 to the fiber channel chip 16 or the PCI bridge module 40 (refer to an arrow A11), as shown in FIG. 6.
In response to the assertion of the REQ64 signal, the fiber channel chip 16 or the PCI bridge module 40 asserts an ACK64 signal to notify the interface module-LSI 14 that the fiber channel chip 16 or the PCI bridge module 40 confirms the 64-bit transfer mode connection setting request (refer to an arrow A12).
In response to the assertion of the ACK64 signal, data transfer in the 64-bit transfer mode is initiated between the interface module-LSI 14 and the fiber channel chip 16 or the PCI bridge module 40 through the PCI buses 18, or 51 or 52 (refer to an arrow A13).
However, there is a case where the operation timing of a signal in relation to the mode setting sequence is fluctuated due to abnormality of the LSI or the like of the apparatus while the above mode setting sequence is run, and not the 64-bit transfer mode but the 32-bit transfer mode is unusually set. Such situation (an operation of the interface module 10 or 20 performed when abnormality occurs) will be next described with reference to a sequence diagram shown in FIG. 7.
In an example shown in FIG. 7, the interface module-LSI 14 asserts the REQ64 signal so that the request to set a connection in the 64-bit transfer mode is notified from the interface module-LSI 14 to the fiber channel chip 16 or the PCI bridge module 40 (refer to an arrow A21), like the sequence described above with reference to FIG. 6.
When a situation in which the ACK64 signal from the fiber channel chip 16 or the PCI bridge module 40 is not asserted, or the asserted status is not transmitted to the interface module-LSI 14 due to occurrence of abnormality such as a fluctuation in operation timing although the ACK64 signal is asserted occurs (refer to an arrow A22), the ACK64 signal remains unasserted in the interface module-LSI 14. Complying with this, data transfer is initiated not in the 64-bit transfer mode but in the 32-bit transfer mode between the interface module-LSI 14, and the fiber channel chip 16 or the PCI bridge module 40 through the PCI buses 18, or 51 or 52 (refer to an arrow A23).
Even though data transfer is carried out in not the 64-bit transfer mode but the 32-bit transfer mode, no problem in the specifications occurs in a system in the present condition. For this, the system does not have a means of detecting such the condition (ineffective data transfer status), thus such the condition cannot be detected or remains unsolved. Japanese Patent Laid-Open Publication No. 61-196353 and Japanese Patent Laid-Open Publication No. 7-98675 disclose inventions relating to bus expansion, both of which cannot detect or solve the situation (ineffective data transfer status) described above with reference to FIG. 7.
When data transfer in the 32-bit transfer mode is executed as above, the transfer width is decreased so that the internal throughput and the processing performance are degraded in the system. There is thus a demand to detect and solve the above ineffective data transfer status when such the status occurs.